Beyond Bandwidth Doubling: Embrace Bit-Flips & Unlock Processing-in-NAND
Title
Beyond Bandwidth Doubling: Embrace Bit-Flips & Unlock Processing-in-NAND
Authors
Maximilian Berens, Yun-Chih Chen, Jian-Jia Chen, and Jens Teubner
Accepted at
41th IEEE International Conference on Data Engineering, ICDE, Data Engineering Future Technologies Track, Hong Kong SAR, China, May 19-23. IEEE, 2025.
Abstract
SSDs offer unprecedented capacity and bandwidth and new PCIe standards promise even more. However, the underlying technology, NAND memory, already struggles with significant heat and power consumption challenges. Just like microprocessors before, NAND also experiences Dark Silicon, preventing performance from improving at the same pace as capacity. Much of the power (and thus heat) within a NAND chip results from transferring data at a high rate, another symptom of a compute-centric style of processing. Therefore, we argue for data-centric Processing-in-NAND (PiN). However, PiN comes with significant challenges, such as limited capabilities and the need to cope with bit-flip errors. Even beyond Processing-in-Memory (PiM), databases may soon have to accept that memory is not error-free, an assumption that comes at a significant cost in power, capacity and performance. Our discussion suggests that no PiN design will serve as a singular, universally applicable solution to the bandwidth problem. Instead, successful integration into database architecture requires carefully identifying PiN-compatible functionality and abstractions, and cooperation with other innovations, such as Computational Storage and CXL. Lastly, we analyze the fundamental error tolerance of Bloom filters and binary sketches as PiM-compatible data structures, which we believe may be of independent interest.
Errata
06.05.2025:
- In the Introduction, the combined power draw of multiple SSDs is incorrectly compared to the TDP of a CPU, not it's actual power draw. In the follow-up sentence, the Micron 6550 is listed with "5-6.25W per lane", but the subsequent formula for the combined power demand is incorrectly normalized by 4 (PCIe lanes). Further, 5W more accurately represents the actual active power draw of the device (as listed by the product description). Hence, instead of "6.25 * 128/4 = 200W", the updated formula should be "5 * 128 = 640W".