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Memory Diplomat (MD)

The project Memory Diplomat is part of the DFG Priority Program 2377 “Disruptive Memory Technologies” and is a joint project with the DAES Group of Jian-Jia Chen at TU Dortmund University.

Modern computing systems abstract memory access to a very narrow interface, which essentially consists of only read and write primitives. Originally meant to ease the programmer’s efforts, the existing interfaces cannot keep up with the memory technologies that we see today and may become the performance obstacle of tomorrow. To illustrate, even widely deployed features, such as deep cache hierarchies or NUMA architectures, require deep a priori knowledge; explicit programming effort; and tailor-made libraries (such as libnuma) to actually leverage the hardware potential (e.g, through cache- or NUMA-aware algorithms). The best existing alternative —which has been attempted many times— is to have the operating system guess application characteristics (with often unsatisfactory results).

With Memory Diplomat, we aim for a memory interface that makes characteristics transparent to hard- and software. With a broadened interface, applications can express their true characteristics or intentions to the Memory Diplomat. The Memory Diplomat, in turn, can leverage this information to get the best out of the actual memory types underneath. The use of this broadened interface remains optional for every application, in which case the underlying operating system can fall back to “guessing” as before.

The Memory Diplomat project officially starts on October 1, 2022.

Publications

  • Maximilian Berens, Yun-Chih Chen, Jian-Jia Chen, and Jens Teubner. Beyond Bandwidth Doubling: Embrace Bit-Flips & Unlock Processing-in-NAND. Accepted at 41th IEEE International Conference on Data Engineering, ICDE, Data Engineering Future Technologies Track, Hong Kong SAR, China, May 19-23. IEEE, 2025.
  • Jan Mühlig, Roland Kühn, and Jens Teubner. Understanding Application Performance on Modern Hardware: Profiling Foundations and Advanced Techniques.  Accepted at 3rd Workshop on Novel Data Management Ideas on Heterogeneous Hardware Architectures (NoDMC), Bamberg, Germany, March 2025.
  • Janina Rau, Daniel Biebert, Christian Hakert and Jian-Jia Chen. Dynamic Write-Mode Fragmentation for Non-Volatile Memory Simulation. Accepted at 3rd Workshop on Novel Data Management Ideas on Heterogeneous Hardware Architectures (NoDMC), Bamberg, Germany, March 2025. GI, 2025.
  • Daniel Biebert, Christian Hakert, and Jian-Jia Chen. Realizing Hardware-Optimized General Tree-Based Data Structures for Heterogeneous System Classes. 2025. arXiv: 2501.17434 [cs.AR].
  • Yun-Chih Chen, Tristan Seidl, Nils Hölscher, Christian Hakert, Minh Duy Truong, Jian-Jia Chen, João Paulo C. de Lima, Asif Ali Khan, Jeronimo Castrillon, Ali Nezhadi, Lokesh Siddhu, Hassan Nassar, Mahta Mayahinia, Mehdi Baradaran Tahoori, Jörg Henkel, Nils Wilbert, Stefan Wildermann, and Jürgen Teich. Modeling and Simulating Emerging Memory Technologies: A Tutorial. 2025. arXiv: 2502.10167 [cs.AR].
  • Roland Kühn, Jan Mühlig, and Jens Teubner. How to Be Fast and Not Furious: Looking Under the Hood of CPU Cache Prefetching.  Proc. of the 20th Int'l Workshop on Data Management on Modern Hardware (DaMoN), Santiago, Chile, June 2024.
  • Christian Hakert, Kuan-Hsun Chen, and Jian-Jia Chen. FLInt: Exploiting Floating Point Enabled Integer Arithmetic for Efficient Random Forest Inference. In: Design, Automation & Test in Europe Conference & Exhibition, DATE 2024, Valencia, Spain, March 25-27, 2024. IEEE, 2024.
  • Christian Hakert, Kay Heider, Junjie Shi, and Jian-Jia Chen. Towards Non-Volatile Memory Wear-Leveling In (Timing)-Critical Systems. In: 2nd Workshop on OPtimization for Embedded and ReAl-time systems (OPERA). 2024.
  • Daniel Biebert, Christian Hakert, Kuan-Hsun Chen, and Jian-Jia Chen. Register Your Forests: Decision Tree Ensemble Optimization by Explicit CPU Register Allocation. In: CoRR abs/2404.06846 (2024). arXiv: 2404.06846.
  • Roland Kühn, Daniel Biebert, Christian Hakert, Jian-Jia Chen, Jens Teubner.  Towards Data-Based Cache Optimization of B+-Trees.  Proc. of the 19th Int'l Workshop on Data Management on Modern Hardware (DaMoN), pages 63-69. Seattle, WA, USA, June 2023.
  • Christian Hakert, Asif Ali Khan, Kuan-Hsun Chen, Fazal Hameed, Jerónimo Castrillón, and Jian-Jia Chen. ROLLED: Racetrack Memory Optimized Linear Layout and Efficient Decomposition of Decision Trees. In: IEEE Trans. Computers 72.5 (2023).
  • Nils Hölscher, Christian Hakert, Hassan Nassar, Kuan-Hsun Chen, Lars Bauer, Jian-Jia Chen, and Jörg Henkel. Memory Carousel: LLVM-Based Bitwise Wear Leveling for Nonvolatile Main Memory. In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 42.8 (2023).
  • Christian Hakert, Roland Kühn, Kuan-Hsun Chen, Jian-Jia Chen, and Jens Teubner. OCTO+: Optimized Checkpointing of B+Trees for Non-Volatile Main Memory Wear-Leveling. In: 10th IEEE Non-Volatile Memory Systems and Applications Symposium, NVMSA 2021, Beijing, China, August 18-20, 2021. IEEE, 2021.

Software

Project Information

Memory Diplomat Students
  • Daniel Biebert (PhD student, DAES Group)
  • Roland Kühn (PhD student, DBIS Group)
Master/Bachelor Theses

Funding

The Memory Diplomat (MD) project is funded by the Deutsche Forschungsgemeinschaft (DFG); priority program SPP 2377.

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