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Seminar "Hardware-accelerated Query Processing"

News

02.12.2019 - Reviewers assigned

31.07.2019 - Topics assigned

09.07.2019 - Homepage uploaded

Next Deadlines

23.12.2019 - Abgabe der zwei Reviews über HotCRP

29.11.2019 - Abgabe der Ausarbeitung über HotCRP

23.12.2019 - Abgabe der drei Reviews

Description

Hardware accelerators are widely used in modern systems. Dedicated coprocessors such as GPUs, Xeon Phis, or FPGAs provide speed-ups over CPUs. Vice-versa modern CPUs integrate accelerators such as SIMD units to process multiple elements per instruction.

Leveraging such hardware accelerators in a beneficial way is a relevant topic for research and industry. Not only the implementation of highly parallel operations, but also the integration with existing systems remains a challenge. The latter due to communication bottlenecks, cross-platform code bases, and off-loading decision making.

This seminar is about hardware acceleration for modern in-memory query processing techniques. In the seminar, we will discuss a range of topics that addresses various hardware accelerators in the context of column-at-a-time processing, vectorized query processing, and query compilation.

Organization

Preliminary Meeting

A preliminary meeting took place on Friday, July 12th 2019 at 9:15 AM in OH14 / room 302.

Information Document

We provide an information document for the seminar. The document describes the course schedule and gives you guidelines for working on the presentation and report. You can download the document here.

Report

The report should follow the ACM Proceedings Templates (LaTeX or Word) with a maximum of 6 pages. Each student reviews two reports from other students.

Talk

The talks are scheduled for 25 to 30 minutes. Each talk is followed by a discussion on the topic and on the presentation.

Topics

A. Coprocessor Communication
  • A1. Gregg et al. Where Is the Data? Why You Cannot Debate CPU vs. GPU Performance Without the Answer. IEEE ISPASS 2011 – pdf
    Timo Gojowczyk
  • A2. Wu et al. Kernel Weaver: Automatically Fusing Database Primitives for Efficient GPU Computation. MICRO 2012 – pdf
    Philipp Koppenstein
  • A3. Funke et al. Pipelined Query Processing in Coprocessor Environments. SIGMOD 2018 – pdf 
    Marcel Ebbrecht
  • A4. Yuan et al. The Yin and Yang of processing data warehousing queries on GPU devices. VLDB 2013 – pdf
    Philipp-Jan Honysz

B. Relational Operator Implementations
  • B1. Karnagel et al. Optimizing GPU-Accelerated Group-By and Aggregation. ADMS 2015 – pdf
    Richard Stewing
  • B2. Jiang et al. Efficient SIMD and MIMD parallelization of hash-based aggregation by conflict mitigation. ICS 2017 – pdf
    Beka Chkopoia

C. Cross-Platform Processing
  • C1. Heimel et al. Hardware-Oblivious Parallelism for In-Memory Column-Stores. VLDB 2013 – pdf
    Dustin Chabrowski
  • C2. Breß et al. Generating custom code for efficient query execution on heterogeneous processors. VLDB J. 2018 – pdf
    Robert Delhougne
D. Operator Placement
  • D1. Karnagel et al. Adaptive Work Placement for Query Processing on Heterogeneous Computing Resources. VLDB 2017 – pdf
    Marius Gunnemann
  • D2. Breß et al. Robust Query Processing in Co-Processor-accelerated Databases. SIGMOD 2016 – pdf
    Jannis Muehlemeyer

E. Parallel Primitives
  • E1. Merrill et al. Single-Pass Parallel Prefix Scan with Decoupled Look-Back. NVIDIA Tech. Report 2016 – pdf
    David Kaester
  • E2. Egielski et al. Massive Atomics for Massive Parallelism on GPUs. ISMM 2014 – pdf
    Julia Moldenhauer

F. FPGAs
  • F1. Teubner et al. Data Processing on FPGAs (Chapters 1, 2, and 3). Synthesis Lectures on Data Management 2013 – pdf
    Pajtim Thaqi
  • F2. Woods et al. Parallel Computation of Skyline Queries. FCCM 2013 – pdf
    Nils Killich
  • F3. Teubner et al. Skeleton Automata for FPGAs: Reconfiguring without Reconstructing. SIGMOD 2012 – pdf
    Fabian Dillkötter
  • F4. Ziener et al. FPGA-based dynamically reconfigurable SQL query processing. TRETS 2016 – pdf (Uninetz)