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Variable Word Length Word-Aligned Hybrid Compression — DaMoN 2020 Reviews

Reviews for paper Variable Word Length Word-Aligned Hybrid Compression, submitted to DaMoN 2020.

Overall Rating: accept as short paper

Reviewer 1

Is the topic of the paper relevant to and important to the DaMoN community?

Yes

Is the paper readable and well organized?

Mostly - the presentation has minor issues and should be improved, but is acceptable

Are the research contributions substantial and novel enough to warrant acceptance?

Yes - the contributions are above the bar

Are the paper's methodology, assumptions, models, and arguments free of serious flaws?

Mostly so - there are some minor issues, but none of them are fatal

Overall rating

Reject

Briefly justify your Overall Rating. Papers with Reject or Strong Reject ratings should have at least one negative score on Q1-Q4.

* Using variable length WAH sounds an intuitive choice for FPGA processors.
* Based on performance results FPGA do not catch up with CPU performance. To fully evaluate performance I would have liked to see sufficient description of the CPU implementation and especially I would like to see whether a parallel and/or vectorised CPU implementation was used.
* I think a diagram that shows the compression ratio versus performance would justify why trading performance for improved compression is worth it.

Detailed Comments

Implementation of variable length WAH on FPGAs sounds like an intuitive match because there is no fixed word size in this architecture. This means smaller word sizes that lead to better compression ratio can be preferred. The authors suggest how to tune the word size in WAH compression towards optimal compression for FPGAs. They measure the compression ratio for different words sizes for uniform and clustered bitmaps. Experiments indicate that for smaller word sizes the compression rate is better. Performance results show lower throughput for FGPA for improved energy efficiency. However, the word size used in the experiments was not the size with the optimal compression ratio, that is part of the paper's motivation.

Typo in keywords: leightweight -> lightweight

If this is a full paper and it is rejected, woud you support its acceptance as a short (2 page) paper?

Yes

Is this paper a good candidate for invitation (of an extended version) to a special "Best of DaMoN" issue of the VLDB Journal?

No

Reviewer 2

Is the topic of the paper relevant to and important to the DaMoN community?

Yes

Is the paper readable and well organized?

Definitely - very clear

Are the research contributions substantial and novel enough to warrant acceptance?

Yes - the contributions are above the bar

Are the paper's methodology, assumptions, models, and arguments free of serious flaws?

Yes

Overall rating

Accept

Briefly justify your Overall Rating. Papers with Reject or Strong Reject ratings should have at least one negative score on Q1-Q4.

The paper shows that the usual approach of using word-aligned compression schemes for bitmaps is not ideal for modern hardware (i.e. FPGAs due to the lack of word-boundaries). The authors demonstrate the benefits of a more fine-granular size regarding compression, and show the potential for an efficient implementation on an FPGA.

The paper is very well written and - while not presenting radically new ideas - makes an interesting contribution for system designers working with bitmaps in the context of FPGAs and other modern hardware.

Detailed Comments

- Section 2.1 and Figure 1 are really great to summarize WAH and lay a great foundation for the remainder of the paper. Nicely done!

- Footnote 1 on page 2 is too long and makes this part of the paper unnecessarily hard to understand. This can be easily fixed by just inlining the footnote.

- It would be great if the authors would open-source their library mentioned in Section 5 to allow other researchers to build on top of it.

- It would be nice if Section 2.1 and Figure 1 would be on the same page (page 2) for better accessibility.

- There are some minor typos:
- Page 1: Abstract: "is a compromise toward" -> towards
- Page 1: Intro: "which is what" -> which are what

If this is a full paper and it is rejected, woud you support its acceptance as a short (2 page) paper?

Yes

Is this paper a good candidate for invitation (of an extended version) to a special "Best of DaMoN" issue of the VLDB Journal?

No

Reviewer 3

Is the topic of the paper relevant to and important to the DaMoN community?

Yes

Is the paper readable and well organized?

Mostly - the presentation has minor issues and should be improved, but is acceptable

Are the research contributions substantial and novel enough to warrant acceptance?

Not really - the novel contributions are too minor

Are the paper's methodology, assumptions, models, and arguments free of serious flaws?

Mostly so - there are some minor issues, but none of them are fatal

Overall rating

Reject

Briefly justify your Overall Rating. Papers with Reject or Strong Reject ratings should have at least one negative score on Q1-Q4.

The paper describes a compression technique based on variable word lengths targeting especially platforms like FPGAs that do not have a word size. It is definitely important and interesting work. However, the paper would benefit from another iteration and much better evaluation before it is eventually published. I do not find it suitable for DaMoN at its current state.

Detailed Comments

The paper spends a lot of space on theoretical evaluation of the algorithm. This evaluation is nice in terms of observing the compression ratios. However, it would have been better if it took much less space and instead (1) the VWLWAH mechanism were described in more detail, and (2) the evaluation had more numbers on real hardware using different word sizes.

Regarding (1), the paper isn't very friendly to people who aren't familiar with WAH compression.

Regarding (2), the authors have the implementation of the presented compression mechanism on real hardware, which is great. However, the paper just shows results with 32bit words, which defeats the purpose of all that was presented in previous sections. Is what is evaluated still like WAH then or are there differences even when you have 32bit words?

End of Section 5 mentions results with 8bit words, but we don't see them on the paper.

I also don't get the results presented in Table 1 very well as they aren't explained very well in this section. I am not entirely sure if this is needed in the paper.

Finally, a more minor point, in Figure 10, it would be nice if you add a note on the graph or as part of the label that indicates ARM runs with clock speed of 1.5GHz. It is a bit confusing now due to x-axis changing frequencies, without referring to paper text.

If this is a full paper and it is rejected, woud you support its acceptance as a short (2 page) paper?

Yes

Is this paper a good candidate for invitation (of an extended version) to a special "Best of DaMoN" issue of the VLDB Journal?

No

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