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Sorting Networks on FPGAs

Publication Details


Sorting Networks on FPGAs


René Müller, Jens Teubner, and Gustavo Alonso


The VLDB Journal, volume 21, number 1, pages 1-23, February 2012.


paper (PDF)




Computer architectures are quickly changing toward heterogeneous many-core systems. Such a trend opens up interesting opportunities but also raises immense challenges since the efficient use of heterogeneous many-core systems is not a trivial problem. Software-configurable microprocessors and FPGAs add further diversity but also increase complexity. In this paper, we explore the use of sorting networks on field-programmable gate arrays (FPGAs). FPGAs are very versatile in terms of how they can be used and can also be added as additional processing units in standard CPU sockets. Our results indicate that efficient usage of FPGAs involves non-trivial aspects such as having the right computation model (a sorting network in this case); a careful implementation that balances all the design constraints in an FPGA; and the proper integration strategy to link the FPGA to the rest of the system. Once these issues are properly addressed, our experiments show that FPGAs exhibit performance figures competitive with those of modern general-purpose CPUs while offering significant advantages in terms of power consumption and parallel stream evaluation.

Publication Log

August 2010

acceptance to The VLDB Journal

April 2010

submission to The VLDB Journal (accept with no further changes)

August 2009

publication of an earlier version of this work at VLDB 2009

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Prof. Dr. Jens Teubner
Tel.: 0231 755-6481