Reviews for paper “Hardware-Accelerated Stream Processing Using FPGAs” (earlier version of Data Processing on FPGAs), submitted to SIGMOD 2009.

**Overall rating:** reject

The paper implements a sliding median operator over 8 data values in a data stream. An FPGA implementation is described, and compared with several CPU-based implementations. The authors claim that their FPGA-based method performs well.

S1. Good description of FPGA background for a DB audience.

S2. Thorough analysis of the architectural design decisions required to implement the proposed operator efficiently on an FPGA.

W1. I am not convinced that the median-of-8 operator is an operator whose performance is worth optimizing in a database context. No evidence is provided that this operator represents a significant component of any real workload. Even if the authors were to get a tenfold improvement, that would have little impact if the operator represented 0.1% of the workload, by Amdahl's law.

W2. There are additional potentially-winning CPU implementations that were not considered in the comparison (see detailed comments).

W3. The authors appear to be unaware of the use of FPGAs in databases by companies such as Netezza.

Medium

High

Low

average interest

Medium

Medium

yes

Weak Reject

No

D1. Elaborating on point W2. There are additional ways you could implement a sliding-window median. In particular, you could take advantage of the work done on the previous iteration so that only one new element has to be moved to the correct place. For example, one could keep the sorted values from the previous window, and when a new value comes in search (scan or binary search) for the expired value and replace it with the new one. Then proceed from this point left or right (as appropriate) as in an insertion sort. This method would require fewer operations on average than full sorting on each iteration. It could even be implemented in a branchfriendly way if conditional branches are the bottleneck.

D2. Taking the mean of the middle two elements seems nonstandard (page 4). It might give unexpected results when users are expecting the median to be an actual data value.

D3. A CPU-based implementation would be easy to modify into a median-of-16 operator, for example, but this seems to be much more of a challenge for an FPGA implementation. I don't see anything special about a window of size 8 in a database context.

Yes

D1. Elaborating on point W2. There are additional ways you could implement a sliding-window median. In particular, you could take advantage of the work done on the previous iteration so that only one new element has to be moved to the correct place. For example, one could keep the sorted values from the previous window, and when a new value comes in search (scan or binary search) for the expired value and replace it with the new one. Then proceed from this point left or right (as appropriate) as in an insertion sort. This method would require fewer operations on average than full sorting on each iteration. It could even be implemented in a branchfriendly way if conditional branches are the bottleneck. Do you agree?

D2. Taking the mean of the middle two elements seems nonstandard (page 4). It might give unexpected results when users are expecting the median to be an actual data value. Is this essential?

Hybrid architectures have a high potential to significantly improve database performance and reliability and the paper's approach to look deeper into the FPGA acceleration is timely and relevant. The prototype showed that FPGA can deliver good acceleration and also pointed out that implementations need to be done knowing all the characteristcs of the technology, otherwise less than optimal results are to be expected.

S1: Identified challenges related to FPGA usage

S2: Practical value in providing approach to addressing the challenges

S3: Relevance of the subject

None

Medium

High

Medium

average interest

Medium

Medium

yes

Accept

No

Nothing beyond the point made in the summary

No

REPLACE THIS WITH YOUR ANSWER

This paper reports the work on using FPGA to accelerate stream processing, using Median Filter as the exmaple and testbed. The paper empirically tests a few important trade-offs in the use of FPGAs; these experiences can potentially benefit other researchers looking at FPGA based implementations.

1. detailed explanation on the problem and their approaches.

2. Rich sets of experiments and results

3. reasonablly well written; informative

1. in general, the paper covers a great deal of detail in FPGA programming for specific operator, but this kind of detail is probably more appropriate for an archtiecture conference but not appropriate for a database system conference.

2. Didn't show FPGA offers signficant perfromance advantge, despite the efforts.

3. didn't have test data on using newer/latest FPGA hardware. So no data actually support that FPGA can be faster than modern CPUs.

4. didn't cover the tradeoffs around flexability and extensbility in using the FPGA approache is.

Low

High

Low

less than 20 people will attend the talk

Medium

Medium

yes

Weak Reject

No

The paper is a good contribution in showing how a specific operator can be implemented using FPGA. However it is not about new operators or new algorithms or new system structures, and it does provide insight as to how such an approach may be incorporated in today’s systems and why the implications could be significant to such systems. For exmaple, how much more effort is needed for parameter changes (slide window size?), and/or different algorithm, compared to other hardware-accelerators or software approaches?

The contribution of this paper would be more appropriately targeted at a different audience.

No

- submission (PDF)
- author feedback
- final paper (PDF) — published at VLDB 2009

- Seite bearbeiten
- Zuletzt geändert am 05.02.2020 17:28
- Datenschutzerklärung
- Impressum